1. Field of the Invention
This invention relates to a liquid crystal display device, and more particularly, to an apparatus for driving a liquid crystal panel to display a uniform luminance in an entire display area of the liquid crystal panel.
2. Description of the Related Art
Conventionally, a liquid crystal display device (hereinafter LCD) includes a liquid crystal panel and a drive circuit for driving the liquid crystal panel. The liquid crystal panel includes a plurality of liquid crystal cells arranged between two glass-like substrates (e.g., an upper glass substrate and a lower glass substrate), and switching elements (e.g., a thin film transistor (hereinafter TFT) array). The drive circuit is typically provided with gate driving integrated circuits (hereinafter xe2x80x9cgate D-ICxe2x80x9d) and data driving integrated circuits (hereinafter xe2x80x9cdata D-ICxe2x80x9d).
In a liquid crystal panel, included circuitry uses a system of storage on gate, as shown in FIG. 1. The circuitry of FIG. 1 includes picture elements (or pixels) that are arranged at intersections of gate lines GL1 to GLn and data lines DL1 to DLm, respectively. Each of the picture elements includes a TFT (MN11 to MNnm) having a gate terminal connected with the gate line GL, a source terminal connected with the: data line DL, a liquid crystal cell (CLC11 to CLCnm) connected between the drain terminal of the TFT and a common voltage line VCL, and an additional capacitor (Cst11 to Cstnm) connected to the drain terminal of the TFT. The additional capacitors Cst21 to Cstnm arranged on the second to nth gate lines GL2 to GLn are also connected to the corresponding previous gate lines GL1 to GLnxe2x88x921, respectively, whereas the additional capacitors Cst11 to Cst1m on the first gate line GL1 are connected to a storage line SL. Each data line DL1 to DLm receives a video signal from a data D-IC, and each gate line GL1 to GLn inputs a gate signal (GS1 to GSn) from a gate D-IC.
Data lines DL1 to DLm are driven using the dot inversion system. In the dot inversion system, a video signal on one data line DLi has a polarity that is opposite to that of the video signals on data lines DLixe2x88x921 and DLi+1, both of which are adjacent to data line DLi. The TFTs MN are selectively turned-on by the gate signal having a pulse shape in order to transmit the video signals on the data lines DL1 to DLm to the liquid crystal cells CLC and the additional capacitors Cst. Then, the liquid crystal cells CLC and the additional capacitors Cst charge the video signal applied from the data line DL through the TFT MN, and maintain the charged signal voltage until the TFTs are turned-on again (i.e., during turning-off of the TFTs). Storage line SL is used as a storage capacitor of the picture elements connected to first gate line GL1. Similarly, the first to (nxe2x88x921)th gate lines GL1 to GLNxe2x88x921 are used as the storage capacitor of the picture elements on the second to nth gate lines GL2 to GLn, respectively.
Referring to FIG. 2, a storage signal SS applied to the storage line SL has a direct current voltage maintaining a constant voltage level (e.g., xe2x88x925V). It is possible to set the voltage level of the storage signal SS equal to the low voltage level of the gate signal GS. Also, gate lines GL1 to GLn receive pulse-shaped gate signals GS1 to GSn, which have trailing edges that gradually descend. This is caused by the gate signal GS being delayed by an output buffer (snot shown) and wiring included in the gare D-IC if a high voltage and a low voltage of the gate signal GS are 20V and xe2x88x925V. respectively, the trailing edge of the gate signal GS consumes about a few milliseconds. More specifically, the trailing esge of the gate signal falls from the voltage level of 20V to the voltage level of xe2x88x924.96V within several microseconds, and then from the voltage level of xe2x88x924.96V to the voltage level of xe2x88x925V in period of a few milliseconds. Because the storage signal SS on the storage line SL maintains a constant voltage level, and because each gate signal GS1 to GSn does not maintain a constant voltage level, esch pixel voltage charged at each picture element on the first gate line GL1 is different from each pixel voltage charged at each picture element on the rest of the gate lines GL2 to GLn.
Such a pixel voltage difference between the gate lines GL1 to GLn will be described in reference to FIGS. 3A and 3B. FIG. 3A shows a waveform of pixel voltage VS1 charged at the picture element on the first gate line GL1, and FIG. 3B represents a waveform of pixel voltage VS2 charged at each picture element on the rest of the gate lines (i.e., the second to last gate lines GL2 to GLn). Referring to FIGS. 3A and 3B, a predetermined level of voltage difference is generated between the pixel voltage VS1 charged at the picture element on first gate line GS1 and the pixel voltage VS2 charged at each pixel on the rest of the gate lines GL2 to GLn, although the data signals having the same voltage are applied to all of the lines. For example, if the data signal to be applied to each picture element on the first gate line GL1 and the rest of the gate lines GL2 to GLn is 5V when the common voltage is fixed at 3V, +2V is the charge at each picture element on the first gate line GL1 and each picture element on the rest of the gate lines GL2 to GLn at first. However, the storage voltage at the picture element on the first gate line GL1 maintains the voltage level of xe2x88x925V after the TFT on the first gate line GL1 is turned off, while the storage voltage at each picture element on the rest of the gate lines GL2 to GLn has the voltage level of xe2x88x924.96V at the moment when the TFTs on the rest of the gate lines GL2 to GLn are turned off. The storage voltage at each picture element on the rest of the gate lines GL2 to GLn decreases gradually and drops down to xe2x88x925V after several milliseconds from the moment when the TFTs on the rest of the gate lines GL2 to GLn are turned off. Since the storage voltage drops down when the TFTs are turned off, the voltage VS2 charged at each picture element on the rest of the gate lines GL2 to GLn also drops by a capacitor coupling effect. If this voltage drop is represented by xcex94V, there exists a voltage difference of xcex94V between the picture elements on the first and second gate lines GL2 and GL2. The voltage difference xcex94V in the above example can be calculated as shown in equation 1 below.
xcex94V=[Cstxc2x7(xe2x88x924.96xe2x88x92(xe2x88x925.0))]/(CLC+Cst+Cgs)xe2x80x83xe2x80x83(1)
In the above equation, xe2x80x9cCLCxe2x80x9d and xe2x80x9cCstxe2x80x9d are the capacitance of the liquid crystal cell CLC and the capacitance of the storage capacitors Cst, respectively, and xe2x80x9cCgsxe2x80x9d represents a parasitic capacitance between the gate and source terminals of TFT MN. The different voltage xcex94V is below 40 mV in the above case. Due to the different voltage xcex94V between the first pixel voltage(VS1) on each picture element of the first gate line GL1 and the second pixel voltage(VS2) on each picture element of the second to nth gate lines, the luminance level on a first line of the liquid crystal panel is different from that of the rest of the lines of the liquid crystal panel.
To overcome the problems described above, preferred embodiments of the present invention provide a liquid crystal panel drive apparatus that displays a uniform luminance level on the entire liquid crystal panel.
A liquid crystal panel drive apparatus according to one preferred embodiment of the present invention applies an alternative current signal to a storage line on the liquid crystal panel.
A liquid crystal panel drive apparatus according to another preferred embodiment of the present invention includes a connector connecting a storage line on a liquid crystal panel with a gate line among a plurality of the gate lines on the liquid crystal panel.
A liquid crystal panel drive apparatus according to still another preferred embodiment of the present invention includes a gate driver for driving a plurality of gate lines on the liquid crystal panel and a storage drive terminal provided near the gate driver, the storage drive terminal driving a storage line on the liquid crystal panel.